## 24/03/2020

### Flip Flop Interview Question Answer - 2

 16 Why NAND gate SR latch is called as active LOW SR latch? The output of the NAND gate SR latch is reverse of the NOR gate SR latch therefore it is called as active LOW SR latch. 17 Why the gated S – R latch is also called as level triggered flip – flops? Gated S – R latch The flip flops of the S – R latch responds only when the clock is HIGH therefore it is also called as level triggered flip – flops. 18 Which is invalid condition for gated S – R latch? S = 1 and R = 1 for NAND gated S – R latch S = 0 and R = 0 for NOR gated S – R latch 19 How to obtain gated D latch from gated SR latch? The SR latch consists of two inputs. The D latch is obtained from SR latch by placing one inverter between S and R terminals. The D latch has only one input. 20 How many input the gated D latch consists of? As the input S and R is complement to each other the gated D latch requires only one input. 21 What do you mean by word D in the D – latch? The word D in the D – latch is used for input data. 22 Why the gated D latch is also called as transparent? Gated D latch The output of the gated D latch follows the input when the ENABLE is high therefore it is called as transparent.  When the Enable is high, low D input makes output Q low. Similarly high D input makes output Q high if the Enable is high. 23 When the gated D latch becomes ineffective? When the ENABLE is low, the gated D latch becomes ineffective. 24 Describe the name of different types of edge triggered flip flop. Types of edge triggered flip flop S – R flip flop J – K flip flop D flip flop 25 What is meaning of the clocked flip flop? Clocked flip flop The flip flop using clock signal is called as clocked flip flop. 26 Describe the difference between asynchronous and synchronous digital system. Asynchronous The output of the logic system can change state when one or more input change. Synchronous The output of the logic system can change state which is determined by a clock signal. 27 Explain the term : Positive edge triggered flip flop and negative edge triggered flip flop Positive edge triggered flip flop It is a flip flop in which state transitions take place only at positive going of the clock pulse. i.e. from Low to High It is represented by triangular symbol. Negative edge triggered flip flop It is a flip flop in which state transitions take place only at negative going of the clock pulse. i.e. from High to Low It is represented by triangular with bubble symbol. 28 Write the other name of edge triggered flip flop. Dynamic triggered flip flop 29 Which type of triggering indicates if there is no symbol at the clock input of the flip flop? Level triggering 30 What are Synchronous control inputs? Synchronous control inputs The S and R input of the S – R flip flop is called as synchronous control inputs because the input affect the flip flop’s output only during the positive edge of the clock pulse.

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